1. Field of the Invention
This invention relates to a multicarrier radio transmission system and, in particular, to an error correcting method in the radio transmission system.
Recent radio transmission systems with their increasing transmission capacities tend to use multilevel or multicarrier schemes. They also require forward error correction to improve the system gain. Some synchronization is needed for such error correction. In particular, synchronism must be held where the error rate is as high as about 10.sup.-2.
2. Description of the Prior Art
FIG. 2 is a block diagram of a conventional scheme. In this figure, component 1 is a serial/parallel converter; component 2 is a frame alignment bit and error correction bit addition circuit; component 2A is a frame counter; component 3 is a modulator; and component 4 is a transmitter. These circuits are provided at the transmitting end. Frame alignment bit and error correction bit addition circuit 2, frame counter 2A, modulator 3, and transmitter 4 are provided in two sets.
For example, when a 100 Mb/s signal is fed to serial/parallel converter 1, it is branched into four 25 Mb/s signals. Each combination of two 25 Mb/s signals is fed to the frame alignment bit addition circuit 2, where a frame alignment bit and error correction bit added. The position of frame alignment bit addition is controlled by frame counter 2A provided for each frame alignment bit addition circuit 2.
The signal from each frame alignment bit and error correction bit addition circuit 2 is fed to modulator 3 to achieve 4PSK for example, and is then transmitted on a carrier depending on transmitter 4. In this example, one 100 Mb/s signal is radio transmitted on two separate carriers.
Component 5 is a receiver; component 6 is a demodulator; component 7 is a frame alignment and error correcting circuit; component 8 is a parallel/serial converter. These circuits are provided at the receiving end. Receiver 5, demodulator 6, and frame alignment and error correcting circuit 7 are provided in two sets corresponding to the number of carriers.
The signal on each carrier enters receiver 5, is demodulated by demodulator 6, and is fed to frame alignment and error correcting circuit 7, where frame alignment is established. Error correction is performed using the error correction bit and according to the established alignment position.
The signal from each frame alignment and error correcting circuit 7 is fed to parallel/serial converter 8, which converts the four 25 Mb/s signals into a 100 Mb/s signal.
The above conventional scheme, however, has the following problem. Among two radio transmission lines MC1 and MC2, if line MC2 is considerably deteriorated, frame alignment is lost at frame alignment error correcting line 7 corresponding to circuit MC2. As a result, error correction becomes impossible on the MC2 signal. This causes the error rate of the 100 Mb/s output to be 1/4, thus lowering the system gain.